A typical example of a non-volatile memory (non-volatile semiconductor storage device) which uses an insulating film as a storage node is a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memory. The MONOS memory is composed of a laminated structure of a conductive gate electrode (M), an Si oxide film (O), an Si nitride film (N), an Si oxide film (O), and a semiconductor substrate (S) and stores information by injecting or emitting carriers (electric charge) into or from the Si nitride film having an electric charge holding function.
The Programming method of the non-volatile memory is selected in accordance with the use thereof. For example, in a most typical method, via an extremely thin Si oxide film (tunnel oxide film) positioned in a layer below an Si nitride film which is an electric charge holding film, electrons are subjected to FN (Fowler Nordheim) tunnel injection (write) from a silicon substrate (semiconductor substrate) (hereinafter, referred to as an Si substrate) to the Si nitride film, while FN tunneling emission (erasure) is performed from the Si nitride film to the Si substrate.
An example of the FN writing/erasure method of electrons via the tunnel oxide film (about 2 nm) is disclosed in Japanese Patent Application Laid-Open Publication No. 5-343694 (Patent Document 1), in which an Si nitride film stoichiometrically excessively containing Si is used in order to increase trap density of the electric charge holding film.
Meanwhile, recently, demands for MONOS memories of hot electron writing (injection)/hot hole erasure methods in which rewriting can be performed by low voltages and at high speeds are increasing. The cell structures of the MONOS memories using hot electron injection and hot hole erasure can be broadly divided into two, i.e., a structure in which a memory MONOS transistor, which stores information, and a selective MOS transistor, which selects a cell, are not separated from each other and a structure in which they are separated. For example, a technique of the former method is disclosed in Japanese Patent Application Laid-Open Publication No. 5-110114 (Patent Document 2), and a technique of the latter method is disclosed in Japanese Patent Application Laid-Open Publication No. 2004-186452 (Patent Document 3).
Hereinafter, the structure and operation of a non-volatile memory cell disclosed in Patent Document 3 will be simply described by using FIG. 28.
This non-volatile memory cell is composed of two MOS transistors, i.e., a memory MONOS transistor which constitutes a storage unit and a selective MOS transistor for selecting the storage unit and reading information. This is a so called split-gate type MONOS memory, and both the transistors generally use N-type transistors. Hereinafter, the memory MONOS transistor and the selective MOS transistor are referred to as a memory transistor and a selective transistor, respectively.
The memory transistor and the selective transistor are formed in an active region separated by an isolation region 302 formed in an Si substrate 301. The selective transistor has a control gate electrode 304 via a gate insulating film 303 formed on the Si substrate 301. The memory transistor is formed by the side wall which is in the left side of the control gate electrode 304 in the drawing, and a sidewall 311 is formed in the side wall which is in the right side in the drawing.
A drain region (diffusion layer) 310 of the selective transistor is connected to a bit line, and the control gate electrode 304 is connected to control gate wiring. On the other hand, a source region (diffusion layer) 309 of the memory transistor is connected to a common line, and a memory gate electrode 308 is connected to a word line. Note that, since the names of the source region 309 and the drain region 310 are different depending on the voltage relation during a reading operation, they are sometimes called by the opposite names.
Herein, since there are two gate electrodes, the gate electrode of the selective transistor is described as a control gate electrode, and the gate electrode of the memory transistor is described as a memory gate electrode.
A capacitance insulating film of the memory transistor is composed of a three-layer film. It is composed of, from the surface side of the Si substrate 301, an Si oxide film (first layer film) 305, an Si nitride film (second layer film) 306, and an Si oxide film (third layer film) 307. The film thicknesses of the first layer film to the third layer film are about 6 nm to 7 nm, about 8 nm to 9 nm, and about 7 nm to 8 nm, respectively. In the above described memory transistor, the Si nitride film 306 which is the second layer film is an electric charge holding insulating film having a carrier holding function and captures carriers (electric charge) in a trap level which is present in a depth of about 1.4 eV to 1.6 eV from the conduction band or the valence band of the Si nitride film. The Si oxide film 305 of the first layer film and the Si oxide film 307 of the third layer film are potential barrier films and prevent leakage of carriers from the Si nitride film 306 to outside and inflow of carries from outside.
Generally, in formation of the Si oxide film 305 of the first layer film, a silicon oxide film obtained by subjecting the Si substrate 301 to heat treatment in an oxidizing atmosphere is employed. In formation of the Si nitride film 306 of the second layer film, chemical vapor deposition (CVD method: Chemical Vapor Deposition) using dichlorosilane (SiH2Cl2) and ammonia (NH3) as raw material gases is employed, and ammonia that is five times or more the flow rate of dichlorosilane is introduced. Formation of the Si oxide film 307 of the third layer film can employ a thermal oxidation method and a CVD method; and, in the thermal oxidation method, the Si nitride film 306 is oxidized in an oxidizing atmosphere, thereby forming the Si oxide film 307. On the other hand, in the CVD method, the Si oxide film 307 is deposited on the Si nitride film 306 by using dichlorosilane and nitrous oxide (N2O) as raw material gases. Hereinafter, the Si oxide film 305 which is the first layer film is described as a bottom Si oxide film, and the Si oxide film 307 which is the third layer film is described as a top Si oxide film. Also, since the above described three-layer film is generally referred to as an ONO film, the three-layer film will be also described as an ONO film.
Typical operations of the memory cell structure will next be described. The potential of the source region 309, the potential of the drain region 310, the potential of the control gate electrode 304 of the selective transistor, and the potential of the memory gate electrode 308 of the memory transistor will be described as Vs, Vd, Vcg, and Vmg, respectively.
In a writing operation, for example, Vs=5V, Vmg=10V, Vcg=0.4V, and Vd=0V, and these potentials are applied as pulses, for example, for one microsecond. An extremely large electric field is applied to the surface of the Si substrate 301 that is immediately below the extremely narrow region electrically insulating the selective transistor from the memory transistor. Channel electrons therein accelerated by the electric field become hot electrons, and part of them is drawn into the memory gate electrode 308 side and injected into the Si nitride film 306 by the large electric field of the memory gate electrode 308.
In an erasure operation, for example, Vs=8V, Vmg=−6V, Vcg=0V, and Vd=0V, and these potentials are applied as pulses, for example, for 100 microseconds. In an end of the source region 309, band-to-band tunneling occurs because of an extremely large electric field, and hot holes are generated. Part of the hot holes are drawn to the memory gate electrode 308 side and injected into the Si nitride film 306 by the large electric field of the memory gate electrode 308.
In a reading operation, for example, Vs=0V, Vmg=1.5V, Vcg=1.5V, and Vd=1.5V. In other words, the selective transistor is caused to be in an on state, an potential that is between a threshold value of a write state and a threshold value of an erasure state is applied to the memory gate electrode 308 of the memory transistor. Accordingly, the memory cell to which electrons are injected maintains an off state, while the memory cell to which holes are injected becomes an on state; thus, binary information can be read.
As described above, even when the thickness of the bottom Si oxide film is increased, a MONOS memory using carries of both the electric charge types enables low-voltage and high-speed programming which cannot be realized by the FN injection/FN erasure method.